list p=18F8722, r=DEC
		#include P18F8722.INC


		CONFIG	OSC = HSPLL
;   Oscillator Selection:
;     OSC = LP             LP
;     OSC = XT             XT
;     OSC = HS             HS
;     OSC = RC             RC
;     OSC = EC             EC-OSC2 as Clock Out
;     OSC = ECIO6          EC-OSC2 as RA6
;     OSC = HSPLL          HS-PLL Enabled
;     OSC = RCIO6          RC-OSC2 as RA6
;     OSC = INTIO67        INTRC-OSC2 as RA6, OSC1 as RA7
;     OSC = INTIO7         INTRC-OSC2 as Clock Out, OSC1 as RA7

		CONFIG	FCMEN = OFF
;   Fail-Safe Clock Monitor:
;     FCMEN = OFF          Disabled
;     FCMEN = ON           Enabled

		CONFIG	IESO = OFF
;   Internal External Osc. Switch Over:
;     IESO = OFF           Disabled
;     IESO = ON            Enabled

		CONFIG	PWRT = ON
;   Power-up Timer:
;     PWRT = ON            Enabled
;     PWRT = OFF           Disabled

		CONFIG	BOREN = SBORDIS
;   Brown-out Reset:
;     BOREN = OFF          Disabled
;     BOREN = ON           SBOREN Enabled
;     BOREN = NOSLP        Enabled except Sleep, SBOREN Disabled
;     BOREN = SBORDIS      Enabled, SBOREN Disabled

		CONFIG	BORV = 28
;   Brown-out Voltage:
;     BORV = 46            4.5V
;     BORV = 43            4.2V
;     BORV = 28            2.7V
;     BORV = 21            2.0V

		CONFIG	WDT = OFF
;   Watchdog Timer:
;     WDT = OFF            Disabled
;     WDT = ON             Enabled

		CONFIG	WDTPS = 1
;   Watchdog Postscaler:
;     WDTPS = 1            1:1
;     WDTPS = 2            1:2
;     WDTPS = 4            1:4
;     WDTPS = 8            1:8
;     WDTPS = 16           1:16
;     WDTPS = 32           1:32
;     WDTPS = 64           1:64
;     WDTPS = 128          1:128
;     WDTPS = 256          1:256
;     WDTPS = 512          1:512
;     WDTPS = 1024         1:1024
;     WDTPS = 2048         1:2048
;     WDTPS = 4096         1:4096
;     WDTPS = 8192         1:8192
;     WDTPS = 16384        1:16384
;     WDTPS = 32768        1:32768

		CONFIG	MODE = MC
;   Processor Mode Selection:
;     MODE = EM            Extended Microcontroller mode
;     MODE = MPB           Microprocessor with Boot Block mode
;     MODE = MP            Microprocessor mode
;     MODE = MC            Microcontroller mode


;   External Bus Address Width:
;     ADDRBW = ADDR8BIT    8-bit Address Bus
;     ADDRBW = ADDR12BIT   12-bit Address Bus
;     ADDRBW = ADDR16BIT   16-bit Address Bus
;     ADDRBW = ADDR20BIT   20-bit Address Bus

;   External Bus Data Width:
;     DATABW = DATA8BIT    8-bit Data Bus
;     DATABW = DATA16BIT   16-bit Data Bus

;   External Bus Data Wait:
;     WAIT = ON            Enabled
;     WAIT = OFF           Disabled

		CONFIG	MCLRE = ON
;   MCLR Enable:
;     MCLRE = OFF          Disabled
;     MCLRE = ON           Enabled

		CONFIG	LPT1OSC = OFF
;   T1 Oscillator Enable:
;     LPT1OSC = OFF        Disabled
;     LPT1OSC = ON         Enabled
;
;   ECCP MUX:
;     ECCPMX = PORTH       Multiplexed with RH7:4
;     ECCPMX = PORTE       Multiplexed with RE6:3

		CONFIG	CCP2MX = PORTC
;   ECCP2 MUX:
;     CCP2MX = PORTBE      Multiplexed with RB3
;     CCP2MX = PORTC       Multiplexed with RC1

		CONFIG	STVREN = ON
;   Stack Overflow Reset:
;     STVREN = OFF         Disabled
;     STVREN = ON          Enabled

		CONFIG	LVP = OFF
;   Low Voltage ICSP:
;     LVP = OFF            Disabled
;     LVP = ON             Enabled

		CONFIG	BBSIZ = BB2K
;   Boot Block Size:
;     BBSIZ = BB2K         2Kb Boot Block
;     BBSIZ = BB4K         4Kb Boot Block
;     BBSIZ = BB8K         8Kb Boot Block

		CONFIG	XINST = OFF
;   XINST Enable:
;     XINST = OFF          Disabled
;     XINST = ON           Enabled

		CONFIG	DEBUG = OFF
;   Background Debugger Enable:
;     DEBUG = ON           Enabled
;     DEBUG = OFF          Disabled

		CONFIG	CP0 = OFF
;   Code Protection Block 0:
;     CP0 = ON             Enabled
;     CP0 = OFF            Disabled

		CONFIG	CP1 = OFF
;   Code Protection Block 1:
;     CP1 = ON             Enabled
;     CP1 = OFF            Disabled

		CONFIG	CP2 = OFF
;   Code Protection Block 2:
;     CP2 = ON             Enabled
;     CP2 = OFF            Disabled

		CONFIG	CP3 = OFF
;   Code Protection Block 3:
;     CP3 = ON             Enabled
;     CP3 = OFF            Disabled

		CONFIG	CP4 = OFF
;   Code Protection Block 4:
;     CP4 = ON             Enabled
;     CP4 = OFF            Disabled

		CONFIG	CP5 = OFF
;   Code Protection Block 5:
;     CP5 = ON             Enabled
;     CP5 = OFF            Disabled

		CONFIG	CP6 = OFF
;   Code Protection Block 6:
;     CP6 = ON             Enabled
;     CP6 = OFF            Disabled

		CONFIG	CP7 = OFF
;   Code Protection Block 7:
;     CP7 = ON             Enabled
;     CP7 = OFF            Disabled

		CONFIG	CPB = ON
;   Boot Block Code Protection:
;     CPB = ON             Enabled
;     CPB = OFF            Disabled

		CONFIG	CPD = OFF
;   Data EEPROM Code Protection:
;     CPD = ON             Enabled
;     CPD = OFF            Disabled

		CONFIG	WRT0 = OFF
;   Write Protection Block 0:
;     WRT0 = ON            Enabled
;     WRT0 = OFF           Disabled

		CONFIG	WRT1 = OFF
;   Write Protection Block 1:
;     WRT1 = ON            Enabled
;     WRT1 = OFF           Disabled

		CONFIG	WRT2 = OFF
;   Write Protection Block 2:
;     WRT2 = ON            Enabled
;     WRT2 = OFF           Disabled

		CONFIG	WRT3 = OFF
;   Write Protection Block 3:
;     WRT3 = ON            Enabled
;     WRT3 = OFF           Disabled

		CONFIG	WRT4 = OFF
;   Write Protection Block 4:
;     WRT4 = ON            Enabled
;     WRT4 = OFF           Disabled

		CONFIG	WRT5 = OFF
;   Write Protection Block 5:
;     WRT5 = ON            Enabled
;     WRT5 = OFF           Disabled

		CONFIG	WRT6 = OFF
;   Write Protection Block 6:
;     WRT6 = ON            Enabled
;     WRT6 = OFF           Disabled

		CONFIG	WRT7 = OFF
;   Write Protection Block 7:
;     WRT7 = ON            Enabled
;     WRT7 = OFF           Disabled

		CONFIG	WRTB = ON
;   Boot Block Write Protection:
;     WRTB = ON            Enabled
;     WRTB = OFF           Disabled

		CONFIG	WRTC = ON
;   Configuration Register Write Protection:
;     WRTC = ON            Enabled
;     WRTC = OFF           Disabled

		CONFIG	WRTD = OFF
;   Data EEPROM Write Protection:
;     WRTD = ON            Enabled
;     WRTD = OFF           Disabled

		CONFIG	EBTR0 = OFF
;   Table Read Protection Block 0:
;     EBTR0 = ON           Enabled
;     EBTR0 = OFF          Disabled

		CONFIG	EBTR1 = OFF
;   Table Read Protection Block 1:
;     EBTR1 = ON           Enabled
;     EBTR1 = OFF          Disabled

		CONFIG	EBTR2 = OFF
;   Table Read Protection Block 2:
;     EBTR2 = ON           Enabled
;     EBTR2 = OFF          Disabled

		CONFIG	EBTR3 = OFF
;   Table Read Protection Block 3:
;     EBTR3 = ON           Enabled
;     EBTR3 = OFF          Disabled

		CONFIG	EBTR4 = OFF
;   Table Read Protection Block 4:
;     EBTR4 = ON           Enabled
;     EBTR4 = OFF          Disabled

		CONFIG	EBTR5 = OFF
;   Table Read Protection Block 5:
;     EBTR5 = ON           Enabled
;     EBTR5 = OFF          Disabled

		CONFIG	EBTR6 = OFF
;   Table Read Protection Block 6:
;     EBTR6 = ON           Enabled
;     EBTR6 = OFF          Disabled

		CONFIG	EBTR7 = OFF
;   Table Read Protection Block 7:
;     EBTR7 = ON           Enabled
;     EBTR7 = OFF          Disabled

		CONFIG	EBTRB = ON
;   Boot Block Table Read Protection:
;     EBTRB = ON           Enabled
;     EBTRB = OFF          Disabled




		;01	RE1,WR				CAN9M, 6	DSR,IN
		;02	RE0,RD				CAN9M, 1	CD,IN
		;03	RG0/CCP3			MLW40, 40
		;04	RG1,TX2,CK2			CAN9F, 2	TXD_2
		;05	RG2,RX2,DT2			CAN9F, 3	RXD_2
		;06	RG4,CCP4			MLW40, 39
		;07	MCLR/VPP			RESET, JUMPER
		;08	RG4,CCP5			MLW40, 38
		;09	VSS
		;10	VDD
		;11	RF7,SS				MLW40, 37
		;12	RF6,AN11			MLW40, 36
		;13	RF5,AN10,CVREF		MLW40, 35
		;14	RF4,AN9				MLW40, 34
		;15	RF3,AN8				MLW40, 33
		;16	RF2,AN7,C1OUT		MLW40, 32
		;17	RF1,AN6,C2OUT		MLW40, 30
		;18	RF0,AN5				MLW40, 31
		;19	AVDD
		;20	AVSS
		;21	RA3,AN3,VREF+		VREF+
		;22	RA2,AN2,VREF-		MLW40, 29
		;23	RA1,AN1				MLW40, 28
		;24	RA0,AN0				MLW40, 27
		;25	VSS
		;26	VDD
		;27	RA5,AN4,LVDIN		MLW40, 26
		;28	RA4,T0CKI			MLW40, 25
		;29 RC1,T1OSI,CCP2		MLW40, 24
		;30	RC0,T1OSO,T13CKI	MLW40, 23
		;31	RC6,TX1,CK1			CAN9M, 3	TXD,OUT
		;32	RC7,RX1,DT1			CAN9M, 2	RXD,IN
		;33	RC2,CCP1			MLW40, 22
		;34	RC3,SCK,SCL			MLW40, 21
		;35	RC4,SDI,SDA			MLW40, 20
		;36	RC5,SDO				MLW40, 19
		;37	RB7,KBI3,PGD		MLW40, 18
		;38	VDD
		;39	OSC1,CLKI
		;40	OSC2,CLKO,RA6
		;41	VSS
		;42	RB6,KBI2,PGC		MLW40, 17
		;43	RB5,KBI1,PGM		MLW40, 16
		;44	RB4,KBI0			MLW40, 15
		;45	RB3,INT3			MLW40, 14
		;46	RB2,INT2			MLW40, 13
		;47	RB1,INT1			MLW40, 12
		;48	RB0,INT0			MLW40, 11
		;49	RD7,PSP7			MLW40, 10
		;50	RD6,PSP6			MLW40, 9
		;51	RD5,PSP5			MLW40, 8
		;52	RD4,PSP4			MLW40, 7
		;53	RD3,PSP3			MLW40, 6
		;54	RD2,PSP2			MLW40, 5
		;55	RD1,PSP1			MLW40, 4
		;56	VSS
		;57	VDD
		;58	RD0,PSP0			MLW40, 3
		;59	RE7,CCP2			/LED YELLOW, BOOTLOAD JP
		;60	RE6					/LED RED
		;61	RE5					CAN9M, 9	RI,IN
		;62	RE4					CAN9M, 8	CTS,IN
		;63	RE3					CAN9M, 7	RTS,OUT
		;64	RE2,CS				CAN9M, 4	DTR,OUT

		;MLW40, 2	GND
		;MLW40, 1	+3.3V/+5V


		;VYSTUPY V ROLI BOOTLOADERU
		;RC6, RE3, RE2, RG1 - VSECHNY VE VYSOKE UROVNI
		;RE7,RE6 - LED

		CBLOCK	0
		  COUNTER
		  COUNTER_HI
		  COUNTER_REC
		  COUNTER_REC2LOW
		  COUNTER_REC2HIGH

		  DID
		ENDC

		CBLOCK	0X100
		  BUFFER
		ENDC

		ORG 0x0
  		GOTO	START

		ORG 0x8
		GOTO	0X808

		ORG 0x18
		GOTO	0X818

SEND2
		BTFSS	PIR3,TX2IF
		BRA		SEND2
		MOVWF	TXREG2
		RETURN

RECEIVE2
		BTFSS	RCSTA2,OERR
		BRA		RECEIVE2_NOERR
		BCF		RCSTA2,CREN
		BSF		RCSTA2,CREN
RECEIVE2_NOERR
		BTFSS	PIR3,RC2IF
		BRA		RECEIVE2_NOERR
		MOVF	RCREG2,W
		RETURN

WRITE
		;----
;ERASE
		;ZMAZNE BLOK 64B FLASH PODLE TBLPTR
		BSF		EECON1,EEPGD
		BCF		EECON1,CFGS
		BSF		EECON1,WREN
		BSF		EECON1,FREE
		;BCF		INTCON,GIE
		MOVLW	0X55
		MOVWF	EECON2
		MOVLW	0XAA
		MOVWF	EECON2
		BSF		EECON1,WR
		NOP
		;BSF		INTCON,GIE
		;RETURN
		;----
		;ZAPISE Z BUFFER 64B DO FLASH, TBLPTR POSUNE O 64B
		LFSR	FSR0,BUFFER

		MOVLW	8
		MOVWF	COUNTER_HI

		BSF		EECON1,EEPGD
		BCF		EECON1,CFGS
		BSF		EECON1,WREN

		TBLRD*-
WRITE_LOOP2
		MOVLW	8
		MOVWF	COUNTER
WRITE_LOOP1
		MOVFF	POSTINC0,TABLAT
		TBLWT+*
		DECFSZ	COUNTER,F
		BRA		WRITE_LOOP1

		;ZAPSAT
		;BCF		INTCON,GIE
		MOVLW	0X55
		MOVWF	EECON2
		MOVLW	0XAA
		MOVWF	EECON2
		BSF		EECON1,WR
		NOP
		;BSF		INTCON,GIE

		DECFSZ	COUNTER_HI,F
		BRA		WRITE_LOOP2

		BCF		EECON1,WREN

		MOVLW	.63
		SUBWF	TBLPTRL,F
		MOVLW	0
		SUBWFB	TBLPTRH,F
		MOVLW	0
		SUBWFB	TBLPTRU,F

		;VYPSAT NA SERIAK, CO JSEM TO FYZICKY ZAPSAL

		MOVLW	.64
		MOVWF	COUNTER
WRITE_LOOP3
		TBLRD*+

		MOVF	TABLAT,W
		CALL	SEND2

		DECFSZ	COUNTER,F
		BRA		WRITE_LOOP3

		;MOVLW	.64
		;SUBWF	TBLPTRL,F
		;MOVLW	0
		;SUBWFB	TBLPTRH,F
		;MOVLW	0
		;SUBWFB	TBLPTRU,F


		RETURN


START
		;TESTNU JUMPER PRO BOOTLOAD
		BTFSC	PORTE,7
		GOTO	0X800		;NECHCE SE BOOTLOADER

BOOTLOAD
		MOVLW	B'00000111'
		MOVWF	CMCON

		MOVLW	B'00000000'
		MOVWF	LATA

		MOVLW	B'00000000'
		MOVWF	LATB

		MOVLW	B'01000000'
		MOVWF	LATC

		MOVLW	B'00000000'
		MOVWF	LATD

		MOVLW	B'00001100'	;OBE LED SVITI
		MOVWF	LATE

		MOVLW	B'00000000'
		MOVWF	LATF

		MOVLW	B'00000010'
		MOVWF	LATG



		MOVLW	B'11111111'
		MOVWF	TRISA

		MOVLW	B'11111111'
		MOVWF	TRISB

		MOVLW	B'10111111'
		MOVWF	TRISC

		MOVLW	B'11111111'
		MOVWF	TRISD

		MOVLW	B'00110011'
		MOVWF	TRISE

		MOVLW	B'11111111'
		MOVWF	TRISF

		MOVLW	B'11111101'
		MOVWF	TRISG


;		;NAHODIT ADC
;		MOVLW	 B'00000001'	;ADC ON, AN0
;		MOVWF	 ADCON0
;
;		MOVLW	 B'00010011'	;Vref+, 11xADC
;		MOVWF	 ADCON1
;
;		MOVLW	 B'10000110'	;right justified, Fosc/64
;		;MOVLW	 B'10000111'	;right justified, FRC
;		MOVWF	 ADCON2

		;ADC VYPNOUT
		MOVLW	B'00001111'
		MOVWF	ADCON1


		MOVLW	.12			;115200bps pri 24MHz taktovani
		MOVWF	SPBRG1
		BSF	TXSTA1,BRGH
		BSF	TXSTA1,TXEN

		BSF	RCSTA1,CREN
		BSF	RCSTA1,SPEN

		;UART1 OK

		MOVLW	.12			;115200bps pri 24MHz taktovani
		MOVWF	SPBRG2
		BSF	TXSTA2,BRGH
		BSF	TXSTA2,TXEN

		BSF	RCSTA2,CREN
		BSF	RCSTA2,SPEN

		;UART2 OK

;		BCF	EECON1,EEPGD	;pristupy budou do EEPROM, ne pameti programu
;		BCF	EECON1,CFGS

		;PIC NASTAVEN

		;PRECIST DEVID1
		MOVLW	LOW(0X3FFFFE)
		MOVWF	TBLPTRL
		MOVLW	HIGH(0X3FFFFE)
		MOVWF	TBLPTRH
		MOVLW	UPPER(0X3FFFFE)
		MOVWF	TBLPTRU
		TBLRD*
		MOVFF	TABLAT,DID
		SWAPF	DID,F
		RRNCF	DID,F
		RRNCF	DID,F
		MOVLW	B'00000011'
		ANDWF	DID,F

		MOVLW	LOW(.65536-.2016)
		MOVWF	COUNTER_REC2LOW
		MOVLW	HIGH(.65536-.2016)
		MOVWF	COUNTER_REC2HIGH
		;TED JE NASTAVEN POCET BLOKU PRO 6722 - 128kB

		MOVLW	B'11'
		XORWF	DID,W
		BTFSS	STATUS,Z
		BRA		NO6627
		MOVLW	LOW(.65536-.1504)
		MOVWF	COUNTER_REC2LOW
		MOVLW	HIGH(.65536-.1504)
		MOVWF	COUNTER_REC2HIGH
		;PRO 6627 - 96kB
NO6627
		MOVLW	B'10'
		XORWF	DID,W
		BTFSS	STATUS,Z
		BRA		NO6622
		MOVLW	LOW(.65536-.992)
		MOVWF	COUNTER_REC2LOW
		MOVLW	HIGH(.65536-.992)
		MOVWF	COUNTER_REC2HIGH
		;PRO 6622 - 64kB
NO6622
		MOVLW	B'01'
		XORWF	DID,W
		BTFSS	STATUS,Z
		BRA		NO6527
		MOVLW	LOW(.65536-.736)
		MOVWF	COUNTER_REC2LOW
		MOVLW	HIGH(.65536-.736)
		MOVWF	COUNTER_REC2HIGH
		;PRO 6527 - 48kB
NO6527

		MOVLW	LOW(0X0800)
		MOVWF	TBLPTRL
		MOVLW	HIGH(0X0800)
		MOVWF	TBLPTRH
		MOVLW	UPPER(0X0800)
		MOVWF	TBLPTRU

CEKEJSTART
		CALL	RECEIVE2
CEKEJSTART2
		XORLW	'B'
		BNZ		CEKEJSTART

		CALL	RECEIVE2
		XORLW	'o'
		BZ		NEXT1
		XORLW	'o'
		BRA		CEKEJSTART2
NEXT1

		CALL	RECEIVE2
		XORLW	'o'
		BZ		NEXT2
		XORLW	'o'
		BRA		CEKEJSTART2
NEXT2

		CALL	RECEIVE2
		XORLW	't'
		BZ		NEXT3
		XORLW	't'
		BRA		CEKEJSTART2
NEXT3

		CALL	RECEIVE2
		XORLW	'L'
		BZ		NEXT4
		XORLW	'L'
		BRA		CEKEJSTART2
NEXT4

		CALL	RECEIVE2
		XORLW	'o'
		BZ		NEXT5
		XORLW	'o'
		BRA		CEKEJSTART2
NEXT5

		CALL	RECEIVE2
		XORLW	'a'
		BZ		NEXT6
		XORLW	'a'
		BRA		CEKEJSTART2
NEXT6

		CALL	RECEIVE2
		XORLW	'd'
		BZ		NEXT7
		XORLW	'd'
		BRA		CEKEJSTART2
NEXT7
		MOVF	DID,W	;B'00',B'01',B'10' NEBO B'11'
		;MOVLW	'>'
		CALL	SEND2

;LOOP
		;nabrat do pameti 64B, vymaznout blok FLASH a zapsat 64B
		;pote vyslat zpet to, co se precetlo ze zapsane pameti

		;MOVLW	LOW(.65536-.2016)	;32 BLOKU PO 64B NA POCATKU NEBERU
		;MOVWF	COUNTER_REC2LOW
		;MOVLW	HIGH(.65536-.2016)
		;MOVWF	COUNTER_REC2HIGH
REC_LOOP2


		LFSR	FSR0,BUFFER
		MOVLW	.64
		MOVWF	COUNTER_REC
REC_LOOP
		CALL	RECEIVE2
		MOVWF	POSTINC0

		DECFSZ	COUNTER_REC,F
		BRA		REC_LOOP

		CALL	WRITE

		INCFSZ	COUNTER_REC2LOW,F
		BRA		REC_LOOP2
		INCFSZ	COUNTER_REC2HIGH,F
		BRA		REC_LOOP2

;---
		;jeste 16bloku po 64B EEPROM
		BCF		EECON1,EEPGD
		BCF		EECON1,CFGS
		BSF		EECON1,WREN

		MOVLW	.16
		MOVWF	COUNTER_REC2LOW
		CLRF	EEADRH
		CLRF	EEADR
RECEE_LOOP2
		LFSR	FSR0,BUFFER
		MOVLW	.64
		MOVWF	COUNTER_REC
RECEE_LOOP
		CALL	RECEIVE2
		MOVWF	POSTINC0

		DECFSZ	COUNTER_REC,F
		BRA		RECEE_LOOP

		;ZAPSAT 64B EEPROM
		MOVLW	.64
		MOVWF	COUNTER
		LFSR	FSR0,BUFFER
EEWRLOOP
		MOVFF	POSTINC0,EEDATA
		MOVLW	0X55
		MOVWF	EECON2
		MOVLW	0XAA
		MOVWF	EECON2
		BSF		EECON1,WR
		NOP
		BTFSC	EECON1,WR
		BRA		$-2
		INFSNZ	EEADR,F
		INCF	EEADRH,F
		DECFSZ	COUNTER,F
		BRA		EEWRLOOP

		MOVLW	.64
		SUBWF	EEADR,F
		MOVLW	0
		SUBWFB	EEADRH,F

		;PRECIST 64B Z EEPROM A VYSLAT
		MOVLW	.64
		MOVWF	COUNTER
EERDLOOP
		BSF		EECON1,RD
		NOP
		MOVF	EEDATA,W
		CALL	SEND2
		INFSNZ	EEADR,F
		INCF	EEADRH,F
		DECFSZ	COUNTER,F
		BRA		EERDLOOP


		DECFSZ	COUNTER_REC2LOW,F
		BRA		RECEE_LOOP2

		BCF		EECON1,WREN
;---
		CALL	RECEIVE2
		MOVLW	'O'
		CALL	SEND2
		MOVLW	'K'
		CALL	SEND2

		;ZHASNI CERVENOU LED
		BSF		LATE,6

		BRA		$


		ORG	0X800
		BRA	$

		ORG	0X808
		RETFIE

		ORG	0X818
		RETFIE



		;EEPROM
		ORG 0xF00000
		DB	0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF
		DB	0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF
		DB	0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF
		DB	0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF
		DB	0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF
		DB	0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF
		DB	0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF
		DB	0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF
		DB	0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF
		DB	0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF
		DB	0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF
		DB	0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF
		DB	0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF
		DB	0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF
		DB	0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF
		DB	0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF

		DB	0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF
		DB	0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF
		DB	0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF
		DB	0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF
		DB	0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF
		DB	0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF
		DB	0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF
		DB	0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF
		DB	0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF
		DB	0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF
		DB	0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF
		DB	0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF
		DB	0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF
		DB	0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF
		DB	0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF
		DB	0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF

		DB	0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF
		DB	0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF
		DB	0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF
		DB	0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF
		DB	0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF
		DB	0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF
		DB	0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF
		DB	0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF
		DB	0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF
		DB	0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF
		DB	0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF
		DB	0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF
		DB	0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF
		DB	0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF
		DB	0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF
		DB	0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF

		DB	0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF
		DB	0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF
		DB	0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF
		DB	0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF
		DB	0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF
		DB	0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF
		DB	0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF
		DB	0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF
		DB	0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF
		DB	0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF
		DB	0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF
		DB	0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF
		DB	0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF
		DB	0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF
		DB	0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF
		DB	0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF

		END